The present invention relates generally to computer memory, and more specifically, to the detection of memory cells that are stuck in a physical state.
In some memory technologies, a common failure mechanism for a memory cell is for the memory cell to experience a change in its capability to convert to a desired state, typically as a result of too many write attempts. For example, in phase change memory (PCM) it has been documented that after a certain number of write attempts, a memory cell may either fail to “reset” fully or it may become stuck in a very high resistance state as a result of the cell effectively becoming detached from its electrode. In the case of a binary PCM, memory cells experiencing these phenomena may be perceived as “stuck-at set” or “stuck-at reset.” In the case of a multilevel PCM, failing to reset fully may manifest as an inability to reach the higher resistance levels, while being stuck in a very high resistance level may manifest as being stuck in the level with highest resistance.